mitsubishi lsis 2097152-bit (262144-word by 8-bit) cmos static ram mitsubishi electric m5m5v208fp,vp,rv,kv,kr -70l , -85l, -10l , -12l, -70ll, -85ll, -10ll, -12ll '97.3.21 package m5m5v208fp : 32 pin 525 mil sop m5m5v208vp,rv : 32pin 8 x 20 mm2 tsop m5m5v208kv,kr : 32pin 8 x 13.4 mm2 tsop ?single 2.7 ~ 3.6v power supply ?operating temperature of 0 to +70? ?no clocks, no refresh ?all inputs and outputs are ttl compatible. ?easy memory expansion and power down by s1 & s2 ?data retention supply voltage=2.0v ?three-state outputs: or-tie capability ?oe prevents data contention in the i/o bus ?common data i/o ?battery backup capability ?small stand-by current ??????????0.3?(typ.) application small capacity memory units battery operating system handheld communiation tools description the m5m5v208 is 2,097,152-bit cmos static ram organized as 262,144-words by 8-bit which is fabricated using high-performance quadruple-polysilicon and double metal cmos technology. the use of thin film transistor(tft) load cells and cmos periphery results in a high density and low power static ram. the m5m5v208 is designed for memory applications where high reliability, large storage, simple interfacing and battery back-up are important design objectives. the m5m5v208vp,rv,kv,kr are packaged in a 32-pin thin small outline package which is a high reliability and high density surface mount device(smd).two types of devices are available. vp,kv(normal lead bend type package),rv,kr(reverse lead bend type package). using both types of devices, it becomes very easy to design a printed circuit board. feature pin configuration (top view) 1 outline 32p2m-a(fp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a 17 a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 1 dq 2 dq 3 (0v) gnd 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc (3v) a 15 s 2 w a 13 a 8 a 9 a 11 oe a 10 s 1 dq 8 dq 7 dq 6 dq 5 dq 4 gnd m5m5v208rv,kr a 4 a 5 a 6 a 7 a 14 a 16 a 17 vcc a 15 s 2 w a 13 a 8 a 9 a 11 a 2 a 0 dq1 dq2 dq3 dq5 dq6 dq7 dq8 s 1 a 10 oe a 12 a 1 a 3 dq4 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 m5m5v208vp,kv a 11 a 9 a 8 a 13 s 2 a 15 vcc a 17 a 16 a 14 a 12 a 7 a 6 a 5 a 4 w oe a 10 s 1 dq8 dq7 dq6 dq5 dq4 gnd dq3 dq2 dq1 a 0 a 1 a 2 a 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 60? (vcc=3.6v) 10?a (vcc=3.6v) (max) stand-by (max) active (max) power supply current type m5m5v208fp,vp,rv,kv,kr-70l access time 70ns 27ma (vcc=3.6v) m5m5v208fp,vp,rv,kv,kr-85l m5m5v208fp,vp,rv,kv,kr-10l m5m5v208fp,vp,rv,kv,kr-12l 85ns 100ns 120ns m5m5v208fp,vp,rv,kv,kr-70ll 70ns m5m5v208fp,vp,rv,kv,kr-85ll m5m5v208fp,vp,rv,kv,kr-10ll m5m5v208fp,vp,rv,kv,kr-12ll 85ns 100ns 120ns outline 32p3h-e(vp), 32p3k-b(kv) outline 32p3h-f(rv), 32p3k-c(kr)
mitsubishi lsis 2097152-bit (262144-word by 8-bit) cmos static ram mitsubishi electric m5m5v208fp,vp,rv,kv,kr -70l , -85l, -10l , -12l, -70ll, -85ll, -10ll, -12ll '97.3.21 function function table dq 1 dq 2 dq 3 dq 4 v cc (3v) gnd (0v) w oe dq 5 dq 6 dq 7 dq 8 block diagram 24 13 14 15 17 32 16 s 1 22 18 19 20 21 29 262144 words x 8 bits 512 rows x 128 columns x 32 blocks clock generator 8 a 4 7 a 5 6 a 6 5 a 7 4 a 12 3 a 14 2 a 16 1 a 17 31 a 15 12 a 0 11 a 1 10 a 2 23 a 10 25 a 11 26 a 9 27 a 8 28 a 13 a read cycle is executed by setting w at a high level and oe at a low level while s 1 and s 2 are in an active state (s 1 = l ,s 2 = h). when setting s 1 at a high level or s 2 at a low level, the chips are in a non-selectable mode in which both reading and writing are disabled. in this mode, the output stage is in a high-impedance state, allowing or-tie with other chips and memory expansion by s 1 or s 2 . the power supply current is reduced as low as the stand-by current which is specified as icc3 or icc4, and the memory data can be held at +2v power supply, enabling battery back-up operation during power failure or power-down operation in the non- selected mode. the operation mode of the m5m5v208 is determined by a combination of the device control inputs s 1 , s 2 , w and oe. each mode is summarized in the function table. a write cycle is executed whenever the low level w overlaps with the low level s 1 and the high level s 2 . the address must be set up before the write cycle and must be stable during the entire cycle. the data is latched into a cell on the trailing edge of w, s 1 or s 2 , whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. the output enable oe directly controls the output stage. setting the oe at a high level,the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. mode dq icc s 1 w oe non selection write read high-impedance standby active active active high-impedance d in d out h x x l l l l h h x l h s 2 l x h x h h x x non selection high-impedance standby 9 a 3 s 2 30 31 1 2 3 4 20 19 18 17 16 15 14 13 12 11 10 9 7 32 8 24 30 5 6 21 22 23 25 26 27 28 29 * * *pin numbers inside dotted line show those of tsop. 2
mitsubishi lsis 2097152-bit (262144-word by 8-bit) cmos static ram mitsubishi electric m5m5v208fp,vp,rv,kv,kr -70l , -85l, -10l , -12l, -70ll, -85ll, -10ll, -12ll '97.3.21 3 absolute maximum ratings capacitance symbol parameter test conditions pf pf unit max 7 9 typ min limits v i =gnd, v i =25mvrms, f=1mhz v o =gnd,v o =25mvrms, f=1mhz input capacitance output capacitance c i c o dc electrical characteristics (ta=0~70?, vcc= 2.7 ~ 3.6v, unless otherwise noted) symbol parameter v v v limits test conditions unit v ? (ta=0 ~ 70?, vcc= 2.7 ~ 3.6v, unless otherwise noted) * ?.0v in case of ac ( pulse width 30ns ) note 1: direction for current flowing into an ic is positive (no mark). 2: typical value is for vcc = 3v, ta = 25? ma * ?.0v in case of ac ( pulse width 30ns ) ? ? ma v active supply current (cmos-level input) active supply current (ttl-level input) icc 1 icc 2 stand-by current icc 4 v ih high-level input voltage v il low-level input voltage i o output current in off-state icc 3 stand-by current v oh1 high-level output voltage 1 i oh = ?.5ma v oh2 high-level output voltage 2 i oh = ?.05ma v ol low-level output voltage i ol =2ma i i input current v i =0 ~ vcc s 1 =v ih or s 2 =v il or oe=v ih v i/o =0 ~ vcc s 1 =v il ,s 2 =v ih , o ther inputs=v ih or v il output-open 1) s 2 0.2v or 2) s 1 3 vcc-0.2v, s 2 3 vcc-0.2v other inputs=0 ~ vcc s 1 =v ih or s 2 =v il ,other inputs=0 ~ vcc vcc +0.3v 0.6 2.0 ?.3* 2.4 0.33 0.4 ? 25 20 60 10 vcc -0.5v ? 13 10 -l -ll max typ min parameter supply voltage input voltage output voltage power dissipation operating temperature storage temperature unit v v v mw ? ? conditions with respect to gnd ta=25? 700 0 ~ 70 ?65 ~150 ratings symbol vcc v i v o pd topr tstr ?0.5 * ~4.6 ?0.5 * ~ vcc + 0.5 0 ~ vcc (max 4.6) 0.3 27 22 15 12 ma s 1 0.2v, s 2 3 vcc-0.2v , o ther inputs 0.2v or 3 vcc-0.2v,output-open 0.6 1 -20 ~ +70? -20 ~ +70? -20 ~ +40? +25? f= 10mhz f= 5mhz f= 10mhz f= 5mhz
mitsubishi lsis 2097152-bit (262144-word by 8-bit) cmos static ram mitsubishi electric m5m5v208fp,vp,rv,kv,kr -70l , -85l, -10l , -12l, -70ll, -85ll, -10ll, -12ll '97.3.21 4 (2) read cycle (3) write cycle symbol parameter t cr read cycle time address access time unit ns ns ns ns ns ns ns ns ns ns ns ns symbol parameter unit ns ns ns ns ns ns ns ns ns ns ns ns ns limits t a (s 1 ) t a (s 2 ) t a (oe) t dis (s 1 ) t dis (s 2 ) t dis (oe) t en (s 1 ) t en (s 2 ) t en (oe) t v (a) t a (a) limits -10l,ll ac electrical characteristics (1) measurement conditions -12l,ll chip select 1 access time chip select 2 access time output enable access time output disable time after s 1 high output disable time after s 2 low output disable time after oe high output enable time after s 1 low output enable time after s 2 high output enable time after oe low data valid time after address max min max min 120 120 120 60 40 40 40 120 10 10 5 10 write cycle time write pulse width address setup time address setup time with respect to w chip select 1 setup time chip select 2 setup time data setup time data hold time write recovery time output disable time from w low output disable time from oe high output enable time from w high output enable time from oe low max 35 35 min 100 75 0 85 85 85 40 0 0 5 5 max 40 40 min 120 85 0 100 100 100 45 0 0 5 5 vcc 2.7 ~ 3.6v input pulse level v ih =2.2v,v il =0.4v input rise and fall time 5ns reference level v oh =v ol =1.5v output loads fig.1,cl=30pf cl=5pf (for ten,tdis) transition is measured ?00mv from steady state voltage. (for ten,tdis) ................................. ............... ............. ..... ................... including scope and jig 1ttl cl dq fig.1 output load 85 10 10 5 10 min 85 85 85 45 30 30 30 max 70 10 10 5 10 min 70 70 70 35 25 25 25 max -70l,ll -85l,ll -10l,ll -12l,ll -70l,ll -85l,ll 30 30 max 85 60 0 70 70 70 35 0 0 5 5 min 25 25 max 70 55 0 65 65 65 30 0 0 5 5 min t cw t w (w) t su (a) t su (a-wh) t su (s 1 ) t su (s 2 ) t su (d) t h (d) t rec (w) t dis (w) t dis (oe) t en (w) t en (oe) 100 10 10 5 10 100 100 100 50 35 35 35 (ta =0 ~ 70?, vcc= 2.7 ~ 3.6v, unless otherwise noted )
mitsubishi lsis 2097152-bit (262144-word by 8-bit) cmos static ram mitsubishi electric m5m5v208fp,vp,rv,kv,kr -70l , -85l, -10l , -12l, -70ll, -85ll, -10ll, -12ll '97.3.21 t en (w) 5 read cycle write cycle (w control mode) (4) timing diagrams data valid (note 3) (note 3) t a (a) t a (s1) t v (a) t a (s2) t en (s2) t dis (s1) t dis (s2) t a (oe) t en (oe) t dis (oe) (note 3) (note 3) (note 3) (note 3) t cr t h (d) t su (d) dq 1~8 s 1 t su (s1) s 2 oe t su (s2) t su (a-wh) t en (oe) t dis (oe) (note 3) (note 3) (note 3) (note 3) w t w (w) t rec (w) t su (a) t dis (w) t cw t en (s1) w = "h" level a 0~17 dq 1~8 s 1 s 2 oe a 0~17 data in stable
mitsubishi lsis 2097152-bit (262144-word by 8-bit) cmos static ram mitsubishi electric m5m5v208fp,vp,rv,kv,kr -70l , -85l, -10l , -12l, -70ll, -85ll, -10ll, -12ll '97.3.21 6 write cycle ( s 1 control mode) write cycle (s 2 control mode) t su (s1) (note 3) (note 3) t rec (w) t h (d) t cw (note 5) (note 3) (note 3) t su (a) (note 4) t su (d) t h (d) t cw (note 5) (note 3) (note 3) t su (s2) t rec (w) t su (a) (note 4) (note 3) (note 3) t su (d) data in stable data in stable dq 1~8 s 1 s 2 w a 0~17 dq 1~8 s 1 s 2 w a 0~17 note 3: hatching indicates the state is "don't care". 5: when the falling edge of w is simultaneously or prior to the falling edge of s1 6: don't apply inverted phase signal externally when dq pin is output mode. 4: writing is executed while s2 high overlaps s1 and w low. or rising edge of s2, the outputs are maintained in the high impedance state.
mitsubishi lsis 2097152-bit (262144-word by 8-bit) cmos static ram mitsubishi electric m5m5v208fp,vp,rv,kv,kr -70l , -85l, -10l , -12l, -70ll, -85ll, -10ll, -12ll '97.3.21 (ta = 0 ~ 70?, unless otherwise noted) 0.2v t rec (pd) 2.7v s2 0.2v 7 (3) power down characteristics s 1 control mode s 2 control mode power down characteristics (1) electrical characteristics power down set up time power down recovery time (2) timing requirements t su (pd) t rec (pd) symbol parameter ns max typ limits min test conditions unit 0 5 ms 2.7v t su (pd) 0.2v 2.2v t su (pd) 2.7v 2.7v 2.2v t rec (pd) s 1 3 vcc - 0.2v vcc s 1 vcc s 2 symbol parameter v v max typ limits min test conditions unit ? v 2 50 0.2 -ll -l (note 7) 0.3 8 vcc (pd) v i (s1) v i (s2) icc (pd) power down supply voltage chip select input s 1 chip select input s 2 power down supply current note7: icc (pd) = 0.5? (max.) in case of ta = +25? vcc = 3.0v s 2 0.2v or s 1 3 vcc - 0.2v,s 2 3 vcc - 0.2v 2.0 (ta = 0 ~ 70?, unless otherwise noted )
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